`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: data_delay
// Module Name: data_delay
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: delays the pop signal out of the execution controller by two clock cycles 
// 				 to make sure the instruction decoder module reads the correct data from the FIFO.
//					 Combined with two flip flops in the cpu module, the total execution time of a single instruction 
//					 should be 4 clock cycles. 
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module data_delay(
	input clk,
	input i_pop,
	output reg o_pop);
	 
reg q1;
reg q2;

// delay the pop command
always @(posedge clk) begin
	q1 <= i_pop;
	
	o_pop <= q1;
end

endmodule
